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KMC-28A
OverviewThe KMC-28A is a MIL-SPEC noise canceling dynamic mobile microphone with DTMF pad.
Theory Of OperationThe radio and microphone communicate over the DM line (pin 8 on the RJ-45). This signal appears to be both driven and open collector, depending at what point of the sequence it's in. The DM pin connects directly to the radio's microprocessor (IC511, MDAT pin). It is protected by a diode to ground and +5.17, and has a 4.7K pullup to 5.17V (this voltage is according to the radio schematic). The DM line idles at 0V during it's 45ms "quiet time". Regardless if a microphone is attached or not, every 45ms the radio polls the microphone by sending 60 clocks on the DM line. The clocks have a low period of ~11us and a high period of ~17us. The radio drives the DM line to a nominal 4.5V when the microphone is connected, 5V with no microphone. It is unclear if the 0.5V difference occurs in an actual microphone, or is a result of some characteristic of the test jig.
The Q3 transistor inverts DM, providing a 0V to 5V rising edge clock input into IC4 (CD4017) on a falling edge of DM. There is a lot of jitter on the clock, so the radio's microprocessor is probably doing the work, as opposed to a dedicated circuit in the radio. With the logic analyzer, it appears the period changes to about ~8us high and ~20us low. Below is a screen capture of the clocks and resets for IC4 and IC5 (no key pressed).
The method the microphone uses to determine if a key is pressed is, at best, weird. IC4 and IC4 are decade count/dividers with 10 decoded outputs. There are 10 outputs, Q0 through Q9. When first reset, Q0 is high and Q1 through Q9 are low. With each clock, the current Q(n) output goes low, and Q(n+1) goes high. IC4 drives the column of the keypad matrix, and IC5 drives the row.
The radio normally drives DM low. The combined 280K value of R15 and R16 at 5V (18ua) allows DM to be driven to 0 volts. At the start of a scan sequence, DM is driven to 4.5V by the radio. The radio then switches DM to an input for sampling. If no key is pressed and it's not the "end of keypad" condition, DM will drop down to ~3.5V. If Q1 is pulling DM low, then the voltage will be ~0.65V and ~0.55V. This is low enough for the radios microprocessor to detect a "low" condition, and high enough above 0V for Q3 to conduct and provide the clock signal to IC4.
When the radio drives DM low, transistor Q3 inverts it to create a rising edge clock into IC4. After ~8us, the radio drives DM high for ~11us, and then samples DM for ~9us to determine if transistor Q1 is holding it low, indicating there is a pressed key or "end of keypad" condition at the current clock position. If no key is pressed and it's not the "end of keypad" condition, DM will be at ~3.5V. If the a key is pressed, DM will be ~0.55V.
Transistor Q2 is used as a current sensor to determine when an output IC5 has high is sourcing current into an output that IC4 has low. This occurs either when a key is pressed, or the "end of keypad" output (Q5) on IC5 goes high. As transistor Q2 is a PNP transistor, it will not conduct when the base and emitter are at the same potential. When IC5 is sourcing current (key press or "end of keypad"), the base is now lower than the emitter (because of the voltage drop across R22 (1K)) and Q2 conducts. This pulls the collector high, causing Q1 to conduct, pulling DM low. An R/C circuit ensures that DM will stay low at least 4.7us (t = 47K * 100pf). This is likely to make sure DM stays low when the "end of keypad" on IC5 is reached, or possibly as insurance against noise.
The image on the left is Q2's base (top trace) and collector (bottom trace). Notice the base drops slightly when the IC5's Q5 output goes high, and IC5's current draw increases. The right-hand image is with the '1' key being pressed.
The Q5 output of IC4 is used to provide a clock output to IC5 and to simultaneously reset IC4. The Q6 output of IC5 is used to reset IC5.
Assuming a start from a reset state, Q0 of IC4 will be high, as will Q0 of IC5. When DM goes low and causes IC4 to be clocked, Q0 will go low and Q1 will go high. With no keys pressed, each time IC4 is clocked, the current Q(n) output goes low and Q(n+1) goes high. When Q5 goes high, IC4 resets (Q0 high, all others low), and IC5's Q(n) goes low and Q(n+1) goes high. This repeats every repeats every 5 clocks until Q5 of IC6 goes high. After 30 clocks, the keypad matrix has been completely read. The processor appears to do this twice, likely for debounce and noise immunity.
During the detection of "end of keypad", the DM line is being held low by IC5's Q5 output being high. Regardless of the state of IC4, as long as IC5's Q5 is high, it will be sourcing current. The DM line being low for 5 clocks is how the radio "knows" where it is in the scanning sequence. Based on this collection of
logic analyzer captures, the radio processor doesn't actually care where it stops in the scanning sequence. Once it has seen 5 clocks worth of DM being held low, it "knows" it's at the start of a scanning sequence. In fact, the 45ms delay may not be so much a deliberate delay as much as it may be the time it takes for the radio to perform other housekeeping operations. Supporting evidence is the apparent random position of the IC5 reset relative to the start of the scan. This technique would also allow the radio to recover should a clock pulse get dropped, or an additional clock pulse be introduced through noise.
The logic analyzer capture below shows the various signals when the '5' key is pressed. In the description below, the green Q1-C trace reflects the state of the DM line.
The '5' key row/column is IC4-Q2 (column) and IC5-Q1 (row). Starting at the center-line of the capture, the 5 clocks worth of IC5-Q5 being active and pulling DM low can be seen, followed by IC5 resetting. When IC5 resets, IC4 has implicitly reset because the rising edge of the output of IC4-Q5 simultaneously reset IC4 and clocked IC5. The next 5 rising edges of IC4-CLK (so named on the capture) is row 1 (keys 1, 2, 3 and A) being scanned. Since none are pressed, DM remains high. On the 5th edge, IC4 is reset and IC5 is clocked, resulting in IC4-Q0 going high (an unused output) and IC5-Q0 going low while IC5-Q1 goes high.
Now things begin to happen. Because IC4-Q0 is high, IC4-Q1 though IC4-Q9 are low. IC5-Q1 (the '5' key row) is high, there is a current path because IC4-Q2 is low. The 2nd clock causes IC4-Q0 to low and IC4-Q1 to go high. The current path through IC4-Q2 remains, and DM stays low. Now on the 3rd clock, IC4-Q1 goes low and IC4-Q2 goes high. There is no longer a current path, and DM goes high. On the 4th pulse, IC4-Q2 goes low and IC4-Q3 goes high. Again, there is now a current path to ground for IC5-Q1, and DM goes low. Now the radio goes off for 45ms, before generating the 5th pulse (normally, we'd need to look at the next section of the capture, but it's identical to what's shown on the left side, since the '5' key was held down for several seconds). DM remained low for the 45ms duration, and is still low when the radio generates the 5th pulse. The current path to ground through IC4-Q2 remains, and DM remains low. On the 1st pulse of the next group of 5, IC5-Q2 goes low and IC5-Q3 goes high. There are no current paths to ground, so DM remains high until enough clocks occur that IC5-Q5 goes high for 5 clocks, indicating the "end of keypad" condition to the radio.
It's definitely a convoluted bit of logic, setting an output high and stepping it across while looking for a condition where current isn't flowing. While it's rather elegant in not requiring a microprocessor and the associated cost of programming and managing versions, I would have questioned the reliability of sensing the current flow on IC5 to determine if a key is pressed or not. I would have also imagined that component selection and tolerances would play a significant factor in the reliability of the design, although I could well be mistaken.
The entire point of this exercise was to determine if I can emulate this microphone in the
Icom_Mic-O-Matic project. With the sensitivity to timing, it may require a small dedicated PIC12F629 outboard processor, simply to avoid interrupt latency issues on the main processor. If I use an ARM7 class device, it may not be an issue, since the processor would be running on the order of 60Mhz. With a PIC18F2620 class device at 12Mhz, it may not be possible to react fast enough to be reliable.
As a point of interest, below is what the 8 outputs to the keypad matrix looks like.
Some mediocre pictures of the board I build to simulate the microphone DTMF keypad section, since I don't actually have a KMC-28A.
Documents, Schematics, Etc
发表于 2019-9-17 10:03
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